This invention relates to techniques and apparatus for carrying out correction of DC offsets in electronic circuits. This invention is especially suitable for situations where rapid DC offset correction is desirable.
Many electronic circuits require correction of DC offsets. Radio receivers, including direct conversion receivers and Zero IF (ZIF) receivers, along with radio transmitters as well as other types of electronic devices often require that a DC offset be corrected in order to permit proper operation of the device. When a DC offset is present, it can be amplified by direct coupled amplifiers to distort the signal being processed or even saturate the amplifiers"" output at their supply limits, thus rendering the device inoperable. Therefore, DC offsets normally have to be corrected or compensated in some manner.
The requirements for such correction vary depending upon the application. For example, in certain applications for DC offset correction, there is a requirement that the speed of settling the DC offset correction loop be very fast. For example, in GSM radio receivers, the DC offset correction circuit must be settled to within xc2x130 mV maximum total error within 400 xcexcS at the output of the baseband filter. This is a very stringent requirement which has proven challenging to meet. Even under circumstances where rapid correction is not required by a specification, it is desirable to minimize down time and optimize radio performance.